Formal vs Simulation: When, Why, and Where + SSCS Networking Night

Formal vs Simulation: When, Why, and Where
Muhammed Luqman Jukaku, Synopsys
Abstract: As modern SoCs continue to grow in complexity, verification teams face increasing pressure to achieve higher quality, faster coverage closure, and shorter time to market. While simulation remains the foundation of most verification flows, formal verification has emerged as a powerful complementary technique for uncovering deep corner case bugs, proving critical properties, and improving overall verification confidence. Yet many teams still struggle with practical questions: When should formal be used? Where does simulation scale better? And how can both methodologies work together effectively? This talk presents a practical industry perspective on the strengths, limitations, and real world deployment strategies of simulation and formal verification across IP, subsystem and SoC environments. The session will also discuss emerging trends including AI assisted verification flows, intelligent coverage analysis, and the evolving role of formal techniques in next generation SoC verification.
Speaker biography: Muhammed Luqman Jukaku is a Principal SoC Verification Leader with more than 22 years of experience leading verification activities across IP, subsystem, and SoC for complex high performance semiconductor designs. He currently works at Synopsys, where he leads verification of complex multi-protocol interconnect and subsystem architectures for advanced interface and SoC platforms.
Please register to allow for proper planning.
Parking structure located at 2585 Augustine Dr. 3-hour free parking
Speaker(s): Muhammed,
Agenda:
5:30pm: Networking
6:00pm: Talk
7:00pm: Event ends
2510 Augustine Dr, Santa Clara, CA 95054, Santa Clara, California, United States, 95054