2025 Silicon Valley Area Workshop on EMC Design of High-Speed Systems (PAID) + FREE Exhibits + FREE TC10 on Signal and Power Integrity mtg

IEEE EMC Chapter is sponsoring the event but no monetary gain is gained or funded by the chapter.
Location: Cadence Design Systems, Bldg 5, 2655 Seely Ave., San Jose, CA
Registration link will bring you to the options of the Paid workshop but also to the Free Exhibit/TC events
2025 Silicon Valley Area Workshop on EMC Design of High-Speed Systems workshop with Free Exhibit and Free IEEE EMC Technical Committee 10 on Signal and Power Integrity meeting. For more details on the specific agenda including abstract and speakers' bio, go to https://drive.google.com/file/d/1oHHiBJtyebP1JgqafZF65pR9A0y145uA/view?usp=sharing
Agenda:
Agenda
Table-top Vendor Exhibit in Lobby from 10:20 AM – 2:25 PM (FREE)
Vendors are still signing up and already include Rohde and Schwarz, PCB Automation, Nexperia, Cadence Design Systems, PacketMicro, and Clear Signal Solutions
8:30 AM Light breakfast and registration
9:00 AM Welcome remarks and introductions Electromagnetic Compatibility
9:10 AM EMC Applications of 3D Printable Materials
Dr. Victor Khilkevich, Missouri Univ. of Sci. and Tech.
9:45 AM Model-based EMC Analysis and Diagnosis towards Design-for-EMC
Dr. Dipanjan Gope, SimYog Technology and Indian Institute of Science
10:20 AM Break and vendor table-top show (FREE)
10:45 AM Modeling ESD Protection for High-Speed Applications
Dr. Daryl Beetner, Missouri Univ. of Sci. and Tech.
11:20 AM Round Table Discussion – Future directions and challenges in EMC
11:50 AM Lunch
12:50 PM Challenges and Opportunity for Data Center Generation and Distributions
Dr. Zhiping Yang, PCB Automation
1:25 PM Machine Learning-Assisted Power Delivery Network Design
Dr. Chulsoon Hwang, Missouri Univ. of Sci. and Tech.
2:00 PM Break and vendor table-top show (FREE)
2:25 PM Challenges with next generation interconnect solutions
Stephen Scearce, Amphenol
3:00 PM Round Table Discussion – Future directions and challenges in SIPI for High-
Speed Systems
3:30 PM Happy Hour sponsored by Cadence Design Systems (FREE)
IEEE EMC Mini Seminar-Paper Series Sponsored by IEEE EMC Society Technical
Committee 10 on Signal and Power Integrity (FREE)
3:30PM~4PM: Machine Learn fro EMC/SI/PI-Blackbox, Physics Recovery and Decision Making. by Lijun Jiang. Professor of MST
4PM~4:30PM: CVRM with Feedback for Platform PDN PI Design. by Kinger Cai of Arm
4:30PM~5PM: Developing an open S-parameter visualizer with assistance from AI. by Giorgi Maghlakelidze of nVidia.
5PM~5:30PM: Machine learning model for a trace referenced to meshed ground planes. by Xiaoyan Xiong of Cadence.
4:00 PM End of program
Bldg: 5, 2655 Seely Ave., San Jose, California, United States, 95134