Events

PLEASE NOTE THAT THIS IS FOR CHAPTER OFFICERS OF SANTA CLARA VALLEY SECTION, SAN FRANCISCO SECTION AND OAKLAND-EAST BAY SECTION ONLY Greetings! This year's officer training is being conducted for officers of San Francisco Bay Area Council at the Plug and Play Tech Center in San Jose, CA. This is meant to provide the Chapter officers with training related to the different aspects of the chapter operations. Below are some of the topics that will be covered in the training: 1. vTools 2. Concur Expense 3. Nextgen banking and reporting 4. Senior member elevation program 5. How to run an effective chapter 6. Web presence More detailed agenda will be shared soon along with presenter details. Please register using the link and save the date for the officer training. Room: 2nd floor, Silicon Valley Room, Bldg: Plug and Play Tech Center, 440 N Wolfe Rd, Sunnyvale, California, United States, 94085

This is a hybrid in-person and online event. Pre-registration is required for either. In 1984, the Field Programmable Gate Array (FPGA) was invented at Silicon Valley startup Xilinx by its co-founder Ross Freeman. It was not an obviously good technology as it had serious drawbacks in speed, cost, power, and capacity. However, its novel design transformed the technology industry as it rode the wave of Moore’s Law. As this transformation was not a straight road, companies that did not recognize fundamental industry changes created by the FPGA fell by the wayside. If companies did not stretch to find new uses for this technology, or did not deploy its resources in building a new ecosystem, they also failed. Xilinx’s FPGA invention led to the major industry transformation of the Fabless semiconductor model, and step-by-step Xilinx navigated this field of potential failure. These steps tell of a company growing from a hyper-lean adrenaline-driven startup to a multi-billion-dollar success story. Not every step was correct, and certainly there was some luck. However, considerable effort was required to achieve that luck, and even more effort to capitalize on it. In this talk, IEEE Fellow Steve Trimberger will discuss change: the changing value of semiconductor scaling, the changing needs of EDA, the changing barriers to entry, the changing application of the technology, and the changing role of consultants and corporate relationships over the course of many years. These changes got us to 2026 – what change is next? Please note that an IEEE Milestone for the FPGA will be dedicated on Thu, March 12. Information about attending its dedication online will be available soon. Speaker(s): Dr. Steve Trimberger, 925 Thompson Place, Sunnyvale, California, United States, 94085, Virtual: https://events.vtools.ieee.org/m/534657

Ian Walker of GMW Associates will review the development of projected-field electromagnets for device testing. Speaker(s): Ian, Agenda: 6:30 – 7:00 Socializing and Networking at Quadrant 6:55 Zoom session will be online with Waiting Room 7:00 – 7:45 Lecture begins, online and in person 7:45 – 8:00 Questions and Answers 1120 Ringwood Ct., San Jose, California, United States, 95131, Virtual: https://events.vtools.ieee.org/m/535158

Celebrate International Women's Day 2026 with our virtual panel "Give to Gain: Investing in Women to Strengthen Leadership and Innovation." This engaging international dialogue brings together leaders from higher education, engineering, and IEEE WIE to explore how investing in women creates stronger leadership pipelines and accelerates innovation in STEM and beyond. Virtual: https://events.vtools.ieee.org/m/543770

[]Students and aspiring engineers are invited to attend a controls information session hosted by Nor-Cal Controls Energy Solutions a California-based control systems integrator specializing in SCADA and energy management solutions for utility-scale solar and battery energy storage projects. This event will introduce attendees to the fundamentals of control systems engineering as well as career paths within the field. Representatives from the company will provide insight into current industry trends, share real-world project experiences, and discuss opportunities. The session offers a valuable opportunity for participants to expand their understanding of the controls field while connecting directly with industry professionals. Room: 1217, Bldg: TEB, Sacramento State University, Sacramento, California, United States, Virtual: https://events.vtools.ieee.org/m/544199

Join us for a talk on how SmartNICs and RDMA Power AI in the Cloud, check out an Embodied AI demo and get insights into the state of the Chapter. Training modern Large Language Models (LLMs) requires tens of thousands of GPUs acting as a single "AI Supercomputer." To build this "AI Hypercomputer," we must first address the CPU bottlenecks of traditional general-purpose networking. This talk begins by analyzing why standard TCP/IP processing limits Model Training performance and introduces the concept of "Kernel Bypass" and the role of SmartNICs in offloading network processing from the host CPU. We will explore why modern AI clusters have moved toward hardware offloads (like RDMA) to achieve the high throughput and low latency required for GPU-to-GPU communication. We will also discuss the specific challenges of running lossless transport protocols over lossy Ethernet, where congestion and packet drops can cause severe performance degradation ("tail latency") in large-scale training jobs. The session concludes by analyzing the architectural design patterns required to optimize flow control and ensure reliable delivery in massive AI infrastructure environments. Demo: Comparing Reinforcement Learning with Imitation Learning for Autonomous Warehouse Pick-and-Place using a Robotic Arm This demo simulates a last-meter warehouse picking task, inspired by Amazon/Kiva-style systems but using general-purpose robotics. The experiments explicitly contrast policy-gradient reinforcement learning methods such as PPO with imitation learning inside a physically realistic embodied-AI task built with Isaac Sim. The demo has been designed to expose where each algorithm struggles or excels due to action spaces, partial observability, contact dynamics, and reward structure. These are core issues in embodied AI. This event features a leading industry expert from Google addressing this important topic, followed by a demo on Embodied AI using Isaac Sim / Lab updates on the state of our chapter from the IEEE CIS SCV Chair. 🎤 Talk 1 The Infrastructure of AI: How SmartNICs and RDMA Power the Cloud Speaker: Sujithra Periasamy, Google 🎤 Demo and Talk Comparing Model-Free RL Algorithms for Autonomous Warehouse Pick-and-Place with Mobile Manipulation Speakers: Mayank Kapadia and Dr. Vishnu S. Pendyala, Department of Applied Data Science, College of Information, Data, and Society, San Jose State University 🎤 Talk 2 State of the Chapter Speaker: Dr. Vishnu S. Pendyala, Chair, IEEE CIS Santa Clara Valley Chapter Co-sponsored by: Vishnu S. Pendyala, San Jose State University Speaker(s): Sujithra Periasamy, Dr. Vishnu S Pendyala Room: MLK Room 225, Dr. Martin Luther King, Jr. Library (SJSU), 150 E San Fernando St San Jose, California 95112, San Jose, California, United States, Virtual: https://events.vtools.ieee.org/m/537154

Silicon Metasurfaces for DNA Synthesis Abstract: Ready access to long, accurate, and diverse synthetic DNA is essential for the rapid growth of synthetic biology — a field that genetically programs living cells with new functions. Modern microarray-based DNA synthesizers can generate diverse pools of oligonucleotide (single stranded DNA) sequences in parallel. However, each sequence is produced in limited quantity, and their yields decline with increasing oligo length due to cumulative synthesis errors. These limitations complicate downstream sequence segregation and gene assembly. Attempts to address these challenges by enlarging and spacing synthesis sites farther apart reduce the total number of sequences that can be generated simultaneously, thereby compromising synthesis diversity. [] In this talk, I will introduce B-MOS (Metasurface Oligonucleotide Synthesizer for Engineered Biology) — a novel platform that integrates silicon nanophotonics with solid-phase DNA synthesis to overcome these challenges. B-MOS employs dielectric metasurfaces composed of arrays of high-index and low loss silicon nanoantennas (metasurfaces) patterned on glass as optically programmable synthesis sites. The unique optical signature of each metasurface — its spectral and polarization response — is lithographically encoded into the geometry and orientation of the silicon nanoantennas. Under global illumination, only the metasurface tuned to the wavelength and polarization of the laser absorbs the optical energy and transduces it into highly localized heat to site-selectively activate the synthesis reactions. Tuning the laser enables switching between the synthesis sites without moving parts or complex optical projection systems that lead to alignment errors. As these nanostructures support sharp (high-Q) optical resonances, crosstalk between the synthesis sites is minimized. These sharp resonances allow the dense spectral packing of independently addressable synthesis within the tunable range of the laser, thereby maximizing synthesis diversity. Using temperature as a programmable biochemical control knob, I will demonstrate site-selective enzymatic incorporation of fluorescent nucleotides onto surface-bound DNA using the enzyme terminal deoxynucleotidyl transferase. I will further discuss how integrating B-MOS with microfluidics can enable post-synthesis site-selective amplification and spatial segregation of oligo strands for reliable gene assembly. Finally, I will outline how B-MOS can be extended to RNA and peptide synthesis as well as other enzyme-driven processes. By resonant nanophotonics with programmable biochemical control, B-MOS establishes a scalable physical foundation for high-precision biomolecular manufacturing and next-generation molecular technologies. Speaker: Dr. Punnag Padhy Postdoctoral Scholar Department of Materials Science and Engineering Stanford University AGENDA: Thursday March 19, 2026 11:30 AM: Networking, Pizza & Drinks Noon -- 1 pm: Seminar Please register on Eventbrite before 9:30 AM on Thursday March 19, 2026 $4 IEEE members $6 non IEEE members (discounts for unemployed and students ) Bldg: ==> Use corner entrance: Kifer Road / San Lucar Court ==> Do not enter at main entrance on Kifer Road, EAG Labs, 810 Kifer Road, Sunnyvale, California, California, United States, 95051

Stationary generator sets operated in regions governed by a local environmental review board may be subject to strict emissions regulations. Many of these areas, known as non-attainment zones, have enacted clean air requirements that adhere to the EPA’s Tier 4 standard, effective in 2015. For these stringent applications, Cummins provides Tier 4 gensets that reduce the exhaust constituents to the industry’s lowest emissions standard. This presentation will offer insights on how to design a reliable system that meets local and national code requirements. Speaker(s): Shen Yoon, Agenda: No-host social at 5:30pm Presentation at 6:00pm Dinner at 7:00pm Presentation continues at 7:45pm Adjourn by 8:30pm Zio Fraedo's , 611 Gregory Lane, Pleasant Hill, California, United States, 94523

Speaker(s): Roberto Morabito, Room: 4021, Bldg: Sobrato Campus for Discovery and Innovation, Santa Clara University, 500 El Camino Real, Santa Clara, California, United States, 95054, Virtual: https://events.vtools.ieee.org/m/539764

[]Come join us for lunch, and this important talk - IN-PERSON ONLY Co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate the optical engine (OE) which consists of photonic ICs (PIC) such as the photodiode laser, etc. and the electrical engine (EE) which consists of the electronic ICs (EIC) such as the laser driver, transimpedance amplifier, etc. as well as the switch ASIC (application specific IC). The advantages of CPO are: (a) to reduce the length of the electrical interface between the OE/EE (or PIC/EIC) and the ASIC, (b) to reduce the energy required to drive the signal, and (c) to cut the latency which leads to better electrical performance. In the next few years, we will see more implementations of a higher level of heterogeneous integration of switch, PIC and EIC, whether it is for performance, form factor, power consumption or cost. The content of this lecture: — Silicon Photonics — Data Centers — Optical Transceivers — Optical Engine (OE) and Electrical Engine (EE) — OBO (on-board optics) — NPO (near-board optics) — CPO (co-packaged optics) — 3D Integration of the PIC and EIC — 3D Heterogeneous Integration of PIC and EIC — 3D Heterogeneous Integration of ASIC Switch, PIC and EIC — 3D Heterogeneous Integration of ASIC Switch, PIC and EIC with Bridges — 3D Heterogeneous Integration of ASIC Switch, EIC and PIC embedded in Glass-core Substrate — Various Forms of CPO Speaker(s): John Lau, 673 So Milpitas Blvd, Milpitas, California, United States, 95035

[] Designing Your Early Career: LinkedIn, Resume & Interview Strategy That Works Breaking into today’s competitive job market requires more than technical excellence. It requires clarity, positioning, and the ability to communicate your value with confidence. In this practical and engaging session, career strategist Shima Ghaheri shares how hiring managers actually evaluate candidates — and how students and early-career professionals can strategically present their academic work, projects, internships, and experiences to stand out. Participants will learn how to: - Build a LinkedIn profile that signals clarity and direction - Structure resumes around measurable impact rather than task lists - Approach interviews with preparation and strategic storytelling - Translate technical competence into compelling professional narratives Designed specifically for college students and entry-level professionals, this session offers actionable tools to move from being “qualified on paper” to being selected with confidence. By making hiring systems more transparent, the session aims to reduce opportunity gaps and empower participants to compete through preparation, clarity, and strategy. Whether you are preparing for internships, full-time roles, or your next career move, this session will equip you with frameworks you can implement immediately. Co-sponsored by: IEEE SFV Virtual: https://events.vtools.ieee.org/m/541336

Monthly AdCom meeting: 1. Welcome - Hualiang 2. Symposium status update - Annette/Paul/Hualiang 3. Education outreach status - Masha/Azmat/Hualiang 4. Chapter Storage - Hualiang XXXX NOT 5. Monthly talk preparation - Chandan/Luu 6. Chapter website update - XXXX NOT Venkatesh/Claire/Paul 7. Senior member advancement - Dwayne Xxxx NOT 8: Election 2026 9: Open discussion - All Agenda: Monthly AdCom meeting: 1. Welcome - Hualiang 2. Symposium status update - Annette/Paul/Hualiang 3. Education outreach status - Masha/Azmat/Hualiang 4. Chapter Storage - Hualiang XXXX NOT 5. Monthly talk preparation - Chandan/Luu 6. Chapter website update - XXXX NOT Venkatesh/Claire/Paul 7. Senior member advancement - Dwayne Xxxx NOT 8: Election 2026 9: Open discussion - All Virtual: https://events.vtools.ieee.org/m/544928