Events

IEEE OEB-LMAG, 4Q26 Meeting Visit both the USS Hornet and CA Historical Radio Society Museum! This is one meeting you won’t want to miss! Wednesday, October 14, 2026 (11:50 AM to 2:30 PM PDT) The Oakland East Bay Life Members Affinity Group (OEB LMAG) is hosting an excursion to two historical locations in Alameda CA, including lunch – this is like winning the “daily double”! Our lunch meeting this quarter will be at the USS Hornet Museum, but those who want to spend more time there can come early (at 11:00 AM) for a free docent guided tour of the famous aircraft carrier that recovered the Apollo 11 Astronauts, and their Apollo Capsule, after the first landing of men on the moon, as well as Apollo 12 a few months later. The ship has 20+ restored vintage aircraft from WWII: Grumman FM-2 Wildcat, TBM-3E Avenger, Cold War & Vietnam Era: F-4J Phantom II, F8U-1 Crusader, F-14A Tomcat, F-11 Tiger (cockpit/nose), TA-4J Skyhawk, S-3B VikingHelicopters: SH-3H Sea King, HUP-1 Retriever, SH-2F Seasprite, UH-34D Seahorse, Modern Era: F/A-18C Hornet. After lunch, the excursion will continue with a visit to the birthplace of broadcasting: At the California Historical Radio Society Museum, we be given a tour of the museum that includes a collection that spans about 120 years of radio, wireless communication, and broadcasting history, including vacuum tubes, radios in unusual period casings (snakeskin, neon, even a whisky-bottle design), WWII-era transmitters, CIA com gear, a replica of Amelia Earhart's plane radio, a working telegraph, and vintage televisions (including the largest black-and-white TV ever made) playing classic programs. Please plan to drive, or car pool, to the USS Hornet, docked at Pier 3 in Alameda: USS Hornet - Sea, Air and Space Museum, 707 W Hornet Ave, Alameda, CA 94501 https://maps.app.goo.gl/2YRgoVeC5PcNyNN58 Please plan to arrive no later than 11:50, as lunch will be served at noon! After a leisurely 50 minute lunch, we will depart in the cars we arrived in, and drive to the California Historical Radio Society Museum, about 15 minutes away at: 2152 Central Ave, Alameda, CA 94501 https://maps.app.goo.gl/H15ydMEyjgFxTwUB7 Subsidized fee for OEB Life Members: $30 We also welcome Non-Members, so please bring your spouse or guest(s): $50 Agenda: USS Hornet Museum Tour: 11-Noon Lunch on Board: Noon-1 CHRS Drive and Tour: 1-3 Bldg: Visitor's Entrance, USS Hornet Museum, 707 W Hornet Ave, Alameda, California, United States, 94501

*****This vTools link is for purchase of Vendor Tables ONLY! No walk-in registrations.***** (Limit of 10 vendor tables so do not delay!) Vendor table will be one 6-foot exhibit table. Vendor table includes one (1) attendee ticket. A power strip will be available upon request. For more than one (1) attendee to support the table, please register additional people using the regular attendee link: https://events.vtools.ieee.org/m/562108 Tape, Tacks, Nails may not be applied to walls, ceilings, or doors and are strictly prohibited. Outside food, non-alcoholic and alcoholic beverage are not allowed. IEEE and the Hotel are not responsible for any loss or damage to property belonging to you. Sign-in for attendees and continental breakfast will open at 7:15AM, so please be completely set up by 7:15AM. Vendors are encouraged (voluntary) to bring up to three (3) giveaways to be included in the overall raffle for attendees. This one-day Technical Seminar will cover the fundamentals of electrical design, cable ampacity, protective relaying, and interconnections. The seminar will serve as a primer for engineers and a refresher for experienced engineers. During breaks and lunch there will be opportunities to network with your peers and meet with manufacturers. The registration cost includes continental breakfast, lunch, and refreshments. Please join us in attending this one-day Technical Seminar which will include an impressive list of speakers from IEEE, Eaton, Electrical Reliability Services (a Vertiv Company), ETAP, SEL, and NEMA. Seminar topics will include: - Overview of IEEE 1547-2018, Standard for Interconnection and Interoperability of distributed energy resources (DER) with Electric Power Systems - Electrical Design Fundamentals – Circuit Breaker Applications Understood - Medium Voltage Cable Installations - Cable Ampacity and Sizing Fundamentals Generator - Protective Relaying Fundamentals - NEMA Resources and the NEMA Standards Store Plan to attend this timely, educational Seminar. Registration is now open! Speaker(s): Chase Sun, Chris Lovin, Steve Park, Avelardo Morales , Angel Morales, Mike Stone Agenda: 8:00AM-4:30PM (sign-in opens at 7:15AM) *****Vendors should be set up and ready by 7:15AM.***** DoubleTree by Hilton Hotel Pleasanton at The Club, 7050 Johnson Drive, Pleasanton, California, United States, 94588

This one-day Technical Seminar will cover the fundamentals of electrical design, cable ampacity, protective relaying, and interconnections. The seminar will serve as a primer for engineers and a refresher for experienced engineers. During breaks and lunch there will be opportunities to network with your peers and meet with manufacturers. The registration cost includes continental breakfast, lunch, and refreshments. Please join us in attending this one-day Technical Seminar which will include an impressive list of speakers from IEEE, Eaton, Electrical Reliability Services (a Vertiv Company), ETAP, SEL, and NEMA. Seminar topics will include: - Overview of IEEE 1547-2018, Standard for Interconnection and Interoperability of distributed energy resources (DER) with Electric Power Systems - Electrical Design Fundamentals – Circuit Breaker Applications Understood - Medium Voltage Cable Installations - Cable Ampacity and Sizing Fundamentals Generator - Protective Relaying Fundamentals - NEMA Resources and the NEMA Standards Store Plan to attend this timely, educational Seminar. Registration is now open! For Group Registrations, please list all attendee email addresses under Special Requests. ***** Early-Bird registration closes on July 3, don’t delay!***** (Registration is limited to 100 attendees and must be completed on vTools. No walk-in registrations.) Speaker(s): Chase Sun, Chris Lovin, Steve Park, Avelardo Morales , Angel Morales, Mike Stone Agenda: 8:00AM-4:30PM (sign-in opens at 7:15AM) DoubleTree by Hilton Hotel Pleasanton at The Club, 7050 Johnson Drive, Pleasanton, California, United States, 94588

Materials Science for Quantum Computing Abstract: Quantum technologies have made remarkable advances in recent years, but moving from laboratory demonstrations to useful, large-scale systems remains a formidable engineering challenge. Whether the platform is based on superconducting circuits, semiconductor spins, atoms, ions, or photons, performance and scalability depend critically on materials quality, interfaces, defect control, process uniformity, and integration. Applied Materials is bringing decades of semiconductor manufacturing expertise to these challenges. Its quantum technology program is applying advanced materials engineering, 300-mm wafer processing, precision metrology, integrated photonics, and advanced packaging to improve quantum-device performance and enable larger, more manufacturable systems. Through applying materials engineering, advanced packaging, and next-generation optical materials including metasurfaces, to lower error rates, longer coherence times, and scaling. Applied is also exploring how its capabilities in photonics and materials engineering can support quantum sensing and communications. In this seminar, Dr. Robert Visser, who leads Applied Materials’ quantum technology activities, will discuss how technologies developed to manufacture billions of highly controlled classical devices may help overcome the materials, fabrication, and integration barriers now limiting practical quantum systems. Speaker: Robert J. Visser Vice President of Engineering Technology, Office of the CTO Applied Materials AGENDA: Thursday October 15, 2026 11:30 AM: Networking, Pizza & Drinks Noon -- 1 pm: Seminar Please register on Eventbrite before 9:30 AM on Thursday October 15, 2026 $4 IEEE members $6 non IEEE members (discounts for unemployed and students ) Bldg: ==> Use corner entrance: Kifer Road / San Lucar Court ==> Do not enter at main entrance on Kifer Road, EAG Labs, 810 Kifer Road, Sunnyvale, California, California, United States, 95051

TBD Power system models are essential for planning, analysis, and operational studies, but a model that reproduces a measured response is not necessarily a meaningful model. This presentation examines what makes a power system model meaningful in practice, drawing on extensive experience in model development, parameterization, validation, field testing, and application of generic and vendor-specific models. The presentation will discuss the role of models, the information they can reliably represent, and their inherent limitations. It will also consider how modeling objectives, available data, model structure, and parameter uncertainty affect the interpretation and use of simulation results. Examples from generation, inverter-based resources, and transmission systems will illustrate why meaningful modeling requires more than simply matching measurements. Co-sponsored by: University of California, Riverside Speaker(s): Dr. Pouyan Poubeik (IEEE Fellow), Virtual: https://events.vtools.ieee.org/m/579515

[]This no-cost workshop brings together five industry experts (plus an optional lab tour) to discuss the latest 2.5D/3D/3.5D semiconductor packaging solutions for HPC and AI. It highlights the growing challenges of fault isolation (FI) and failure analysis (FA) in dense interconnects such as hybrid bonding and micro bump arrays, reviews new thermal management options (metallic TIMs, low-temp solders), showcases advanced non-destructive inspection tools (computed laminography and high resolution CT), and introduces cutting edge microscopy techniques (SAM and PiFM) for defect characterization, while outlining emerging FI-FA workflows and tool roadmaps for reliable, scalable AI and data center hardware. Attendees will gain insight into current industry troubleshooting workflows and a forward-looking roadmap of the tools and techniques being developed to address advanced packaging failures. Additionally, the optional lab tour can help the attendees understand the tools and techniques discussed in the lectures. Four guided training talks with small-group interaction: 9:00: Advanced Packaging for AI – Challenges and Roadmaps in Fault Isolation and Failure Analysis 9:30: Metal TIM and Low-Temp Solder Paste for HPC and AI Industry Challenges 10:00: Failure Analysis of Electronic Components for AI and Data Center Infrastructure 10:30: High-Resolution 3D X-Ray Inspection for Advanced Packaging Integration 11:00: Scanning Acoustic Microscopy (SAM) and Photo-induced Force Microscopy (PiFM) for Defect Identification and Characterization in AI Hardware 11:30: lunch, social/networking, and optional lab tours Speaker(s): Yan Li, David Hu, Audrey Chamoire , Jeff Gelb, Austin Barnes Covalent Corp., 925 Thompson Place, Sunnyvale, California, United States, 94085, Virtual: https://events.vtools.ieee.org/m/575155

[]This 2-day symposium focuses on quantified reliability, accelerated testing and probabilistic assessments of the useful lifetime of electronic, photonic, MEMS and MOEMS materials, assemblies, packages and systems in electronics and photonics packaging. This includes failure modes, stress levels, mechanisms, testing schemes, accelerated testing, and environmental stresses. The intent is to bring together electrical, reliability, materials, mechanical, and computer engineers and applied scientists to address the state-of-the-art in all the interconnected fields of electronic and photonic packaging, with an emphasis on various reliabilit-yrelated aspects: design-for-reliability, manufacturing, reliability modeling and accelerated testing. Location: In person at UCLA, and over IEEE WebEx Dates: November 12-13, 2026 Cost: $90 ($75 for IEEE members, $35 for WebEx) through Oct. 16 UCLA, Los Angeles, California, United States

The unprecedented growth of artificial intelligence (AI) is fundamentally transforming data center design. Industry initiatives centered around 800VDC power distribution have emerged as a promising pathway to reduce conversion stages, improve energy efficiency, lower copper usage, and support ultra-high-density computing environments. This presentation will examine the technical and economic drivers behind the transition toward Direct Current (DC) data centers, including increasing AI workloads, growing power demands, and evolving sustainability requirements. It will provide an overview of current industry developments, emerging technologies, and architectural approaches. Speaker(s): Joel Liu, Agenda: No-host social at 5:30pm Presentation at 6:00pm Dinner at 7:00pm Presentation continues at 7:45pm Adjourn by 8:30pm Zio Fraedo's, 611 Gregory Lane, Pleasant Hill, California, United States, 94523